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PARVATHA REDDY BABUL REDDY

VISVODAYA INSTITUTE OF TECHNOLOGY AND SCIENCE’s

VITSPACE

UNIT- I

Computer:-

A computer is an electronic device that manipulates information, or data. It has the ability

to store, retrieve, and process data.

UNIT- I

ARCHITECTURE OF 8086 MICRO PROCESSOR:

Architecture is Divided into two units

1. BIU(Bus InterfaceUnit)

2. EU(Execution Unit)

UNIT- I

The four segment registersin 8086 are

Code segment register (CS)

Data segment register (DS)

Extra segment register (ES)

Stack segment register (SS)

defines the starting address of Code segment

defines the starting address of Data segment

defines the starting address of Extra segment

defines the starting address of Stack segment

UNIT- I

(i) General purposeregisters :

The 8086 has 4- general purpose registers - AX, BX, CX, DX.

All these registers are 16-bit registers used to store 16-bit data

Each register is divided in two 8-bit registers to store 8-bit data

These registers have multiple functions, shown in following Table.

Accumulator

Used

to hold the results of some operations like MUL,

DIV

Base

Index

Used

to hold the offset address (Based addressing)

Counter

Used

as a counter in LOOP and String instructions

Data Index

(or) Extended

Accumulator

Used

to hold a part of result from MUL & DIV.

is also used to hold the 16-bit I/O port address

during

I/O

operation.

(ii) Index Registers :

The Index Registers are used to hold the 16-bit offset address of data stored in Data

and Extra segments.

These registers are used in string operations to hold the offset address of source

string and destination strings.

The SI register holds the offset address of source string in Data Segment.

The DI register holds the offset address of destination string in Extra Segment.

Address of source string

Address of destination string

DS:[SI]

ES:[DI]

The directional flag (DF) selects the increment (or) decrement mode for SI and DI

registers during String instructions manipulation.

UNIT- I

DF = 0 selects increment mode and

DF = 1 selects decrement mode.

(iii) Pointers:

The Pointers are used to hold the offset address relative to data and stack segments.

The base pointer (BP) is used to access data in stack segment.

The stack pointer (SP) is used to hold the address of stack top.

ource Index

is used in string operations to hold the offset address of

source

string in Data segment.

Destination

Index

is used in string operations to hold the offset address of

destination

string in Extra segment.

Base

Pointer

is used to access data the stack segment.

is used to hold the offset address (Based addressing)

Stack Pointer

is used to hold the address of Stack top

(iv)Flag Register / Program Status Word (PSW)

The flag register is used to indicate the status information (or) condition produced by an

instruction execution.

The 8086 has 6- status flags and 3-control flags.

Conditional Flags / Status Flags :

These flags are Set or Reset according to the condition produced by an instruction execution.

The 6- conditional flags of 8086 are CF, PF, AF, ZF, SF, OF

Control flags:

These flags control the operation of the processor.

The 3- control flags of 8086 are DF, IF, TF.

15 12 11 10 9 8 7 6 5 4 3 2 1 0

Figure: Flag register of 8086

Carry Flag (CF) :

It is set to 1, if a carry is generated in Addition (or) Subtraction

Parity Flag(PF) : It is set to 1, if the result of an operation has

Auxiliary carry Flag (AF) : It is used in BCD operations.

It is set to 1, if addition of lower nibble generates a carry.

Zero Flag (ZF) : It is set to 1, if the result of an operation is ZERO

Sign Flag (SF) : It is used with signed numbers only.

UNIT- I

SF=1 for ve results and SF =0 for +ve results

Overflow Flag (OF) : It is set to 1, if the result of a signed operation exceeds the registercapacity.

Directional Flag (DF) :

It is used in string operations to select either increment (or) decrement mode for SI

and DI registers.

DF = 0 selects increment mode and

DF = 1 selects decrement mode.

Interrupt Flag (IF) :

If IF = 1, all the maskable interrupts are recognized and processed by the CPU.

Otherwise, the maskable interrupts are ignored and not processed by CPU.

Trap Flag (TF) :

It is used for debugging purpose

If TF = 1, the processor ent

i.e., the 8086 gets

interrupted automatically at the end of every instruction execution.

Problem :

The content of registers AL and BL are 79H and 88H respectively. Determine the

status of control flags of 8086, after the execution of the instruction ADD AL,BL?

Ans:

= 79 H

0 1 1 1 1 0 0 1

= 88 H

1 0 0 0 1 0 0 0

ADD

AL,

0 0 0 0 0 0 0 1

The status of conditional flags are :

CF = 1 ;

PF = 0;

AF = 1 ;

ZF = 0 ;

SF = 0 ;

OF = 0

UNIT- I

1.1. MEMORY SEGMENTATION

The 8086 uses memory segmentation. In this scheme, the complete 1 MB physical memory is

divided into number of logical segments. The size of each segment is 64 KB in size and is

addressed by one of the segment registers.

The 64 KB logical segment can be located anywhere in 1 MB memory, but the segment will

-bits.

Note that the 8086 does not work the whole 1 MB memory at any given time. However it

works only with four 64 KB segments within the whole 1MB memory.

The four segment registers in BIU define the starting addresses of the four memory

segments with which the 8086 is working at that instant of time. The segment registers in

BIU are used to hold the upper 16-bits of starting address of logical segments. The BIU

inserts -bits of 20-bit starting address.

UNIT- I

Code Segment :

The Code segment is used to store the program instruction codes.

The Code Segment register (CS) is used to hold the upper 16-bits of starting address

-bits of 20-bit starting

address.

For example, if CS=2000H then the Code segment starts at 20000H.

Data Segment :

The Data segment is used to store data variables and constants of the program.

The Data Segment register (DS) is used to hold the upper 16-bits of starting address

of the Data segment.

Data are accessed from Data segment by an Offset address.

The SI, DI, BX, BP registers are used to store the offset address for data segment

Extra Segment :

The Extra segment is an additional data segment.

It is used in String operations to store the destination string.

The Extra Segment register (ES) is used to hold the upper 16-bits of starting address

of the Extra segment.

The SI, DI, BX, BP registers are used to store the offset address for data segment

Stack Segment :

The Stack segment defines the area of memory used for stack.

Stack is a section of memory where the data are accessed in LIFO manner

The stack memory is used to store data, address and status information. It is used by

CPU to store return address during the execution of procedures and ISRs.

The Stack Segment register (SS) is used to hold the upper 16-bits of starting address

of the Stack segment.

The Stack Pointer (SP) register holds the address of Stack top.

Addressing a location within a segment (20-bit Physical address calculation) :

The BIU has a Physical Address Generation Circuit.

It generates the 20-bit physical address by adding Segment base to the Offset address.

The segment register defines the segment base address and

a location within a segment can be addressed by 16-bit offset address as shown in Figure.

For example, if CS= 2000H and IP= 5678H then

Segment base = CS*10

Offset address = IP

= 20000 H

= 5678 H

20-bit Physical address = Segment base + Offset = 25678 H

Figure : 20-bit Physical address calculation

The segment register holds the upper 16-bits of starting address of logical segments. The BIU

inserts -bits of 20-bit starting address.

The Offset address is defined as the distance of operand from the Starting address of the

Segment. The registers used to store the 16-bit offset addresses for various segments are

given in Table.

Segment Segment Register Offset Register

Code

Segment

CS IP

Data Segment DS SI (DI/BX/BP )

Extra Segment ES DI (SI/BX/BP )

Stack Segment SS BP /SP

Advantages of Memory Segmentation :

Allows to access 1 MB memory with 16-bit address.

Allows Separate memory areas for program, data and stack

Provides data and code protection

Provision for relocation of programs and data

Provides a powerful memory management mechanism

Allows the processor to access the data from memory easily and fastly, which

increases the speed of operation

1.2. REGISTER ORGANIZATION OF 8086

The Intel 8086 has a powerful set of registers as shown in figure.

The description of all registers is given in section 1.2

Figure: Register organisation of 8086

1.3. PIN CONFIGURATION OF 8086 :

The pin diagram of 8086 is shown in Figure.

The 8086 consists of 40-pins.

Among these, 21 are multiplexed pins to reduce the number of pins

- A

and

/ S

The 8086 issues two different sets of signals (Pins 24 to 31) in Min. mode and Max. mode.

Min. Mode

Max. Mode

, ALE, , DT/ , M/ , , HLDA, HOLD

QS1, QS0, , , , , RQ/ , RQ/

Figure: Pin diagram of 8086

- AD

(Address / Data lines) :

The lower order 16-address lines (A

- A

) of 8086 are multiplexed with 16- data lines

- D

During T

state of Bus-cycle, the 8086 sends out address on these lines and during

later part of Bus-cycle this multiplexed bus is used as Data bus.

All the above multiplexed pins are at high-impedance state during DMA operation.

/ S

- A

/ S

(Address/Status lines) :

The higher order 4-address lines (A

- A

) are multiplexed with Status lines (S

- S

The S

and S

shows which segment is accessed during current bus cycle.

The S

indicates the status of IF flag.

The S

is always logic 0 and it is not used.

All the above multiplexed pins are at high-impedance state during DMA operation.

S4 S3 Segment

Code Segment

Data Segment

No Segment

Extra Segment

/ S

The 1 MB Physical memory of 8086 is divided into two banks for accessing 16-bitnumbers.

Each bank size is 512 K bytes.

The Bus High Enable signal is used to enable the higher order data bus (D

- D

)

connected to HIGH BANK.

The status signal S

is used by arithmetic co-processor 8087 to determine whether the

CPU is 8086 (or) 8088.

Bank Selected

Both

banks are enabled for 16-bit operation

HIGH

bank is enabled

LOW

bank is enabled

banks are enabled

NMI : Non-Maskable Interrupt:

It is a positive going edge triggered Non-Maskable Interrupt

It cannot be disabled by using software.

This interrupt has highest priority than INTR.

It is a vectored interrupt and the vector address of NMI is 0000:0008 H.

INTR: Interrupt Request :

It is a level triggered maskable Interrupt Request.

It can be disabled by using software i.e., the processor will get interrupted only if

IF=1. Otherwise the processor will not get interrupted even INTR is active.

It is a non-vectored interrupt.

CLK:

The clock input provides the basic timing for µp and bus control activity.

The clock frequencies of different versions of 8086 are 5 MHz, 10 MHz, 8 MHz.

RESET :

It forces all the registers to a predefined values and microprocessor gets reset.

When Reset is active DS, ES, SS, IP and FLAG registers are initialized to 0000H and

CS is initialized to FFFF H.

After Reset, the processor starts execution from FFFF0 H.

READY:

A slow peripheral (or) memory device can be connected to microprocessor through

READY line. It is used to insert wait states in bus cycles as needed to interface with

slow memory & I/O

It is used by the MPU to sense whether the peripheral is ready to transfer data or not

If READY =1, peripheral is ready to transfer data.

If READY=0, the processor WAITS until it goes to HIGH

This input is examined by WAIT instruction.

The 8086 enters into WAIT state after the execution of WAIT instruction.

If = 0, the WAIT instruction functions as NOP

If =1, the processor waits until = 0.

If the co-processor has finished its work then it makes

= 0.

The Read Control Signal is active whenever the processor is ready to read data from

Memory (or) I/O.

MN/ :

OPERATING MODES OF 8086/8088:

The 8086 can be operated in two modes Minimum mode and Maximum mode.

The pin MN/ is used to select the Min. (or) Max. mode of operation.

MN/

= 1 for Minimum mode operation

= 0 for Maximum mode operation

The pins (24-31) issues two different set of signals

mode operations. These pins are described below:

for minimum & maximum

Note : The Min.mode p ins and Max.mode pins are described in sections 1.6 .and 1.7.

Minimum mode:

The min. mode operation is selected by connecting the pin MN/MX to + 5 V

The 8086 is operated in minimum mode in simple systems with a single CPU

In min. mode operation, all the control signals are generated by CPU

It is least expensive way to operate and the operation is similar to 8085A.

Min. Mode signals , ALE, , DT/ , M/ , , HLDA, HOLD

Maximum mode:

The max. mode operation is selected by connecting the pin MN/MX to GND

The 8086 is operated in maximum mode in multi-processor system with more than

one processor.

In max. mode, the control signals are generated by external Bus-controller 8288.

The maximum mode operation is used only when the system contains arithmetic co-

processor such as 8087 numeric co-processor.

Max. Mode signals QS

, QS

, , , , , RQ/ , RQ/

1.4. MINIMUM MODE CONFIGURATION OF 8086 :

The min. mode operation is selected by connecting the pin MN/MX to + 5 V

The 8086 is operated in minimum mode in simple systems with a single CPU

In min. mode operation, all the control signals are generated by CPU

It is least expensive way to operate and the operation is similar to 8085A.

Min. Mode signals , ALE, , DT/ , M/ , , HLDA, HOLD

Clock generator :

It generates a CLK of frequency 5 MHz

It provides the basic timing for µp and bus control activity

It also synchronizes some external signals with the system clock

Address Latches :

Latches are used for de-multiplexing of AD

, A

- A

and

Latches are used for the separation of address and data lines

Address latch enable (ALE) signal is used to enable the Latches

Transceivers/ Bi-directional data buffers

/ S

The Bi-directional data buffers (transmitters/receivers) are used to maintain proper

signal quality. i.e., to increase the fan-out of the system.

The

The DT/

signal is used to enable the bi-directional data buffers

signal controls the flow of data through data buffers

MINIMUM MODE SIGNALS:

( pin-24) :

The interrupt acknowledge signal is a response to the INTR.

It indicates the recognition of an Interrupt Request.

ALE (pin-25) :

The address latch enable signal is used to indicate the presence of valid address

information on multiplexed bus (AD

- AD

)

This signal is used to enable the Address Latches.

The address latches are used to separate the address and data lines.(demultiplexing)

(pin-26) :

The data buffers enable signal is used to enable the bi-directional data bus buffers.

The data bus buffers or transceivers (transmitters/receivers) are used to maintain

proper signal quality.

DT/ (pin-27) :

The data transmit / receive signal is used to indicates the direction of data flow

through the data bus buffers.

DT/ = 1 for transmitting data

DT/ = 0 for receiving data

M/ (pin-28) :

It selects either Memory or I/O operation

M/ = 1 selects memory operation

M/ = 0 selects I/O operation

(pin-29) :

This control signal is active whenever the processor is writing data to Memory or I/O

HOLD & HLDA (pins 31 & 30):

These two signals are used in DMA operation

The HOLD input indicates the processor that other bus master (DMA controller) is

requesting for the use of system bus.

When HOLD =1, the p stops the normal program execution and places address,

data & control buses at high-impedance state and sends HLDA signal to the DMA

controller.

The HLDA signal indicates that the processor has accepted the HOLD request and

the gain control of the system bus is transferred to the DMA controller.

During HLDA =1 , the DMA controller is the master of the system bus.

After removal of HOLD request, the HLDA becomes Low.

Operation

1 0 1

Memory

Read

1 1 0

Memory

Write

0 0 1

I/O

Read

1 1 0

/O Write

Timing diagrams for Min. mode

The working of microprocessor based system can be explained with the help of

Timing diagrams.

The timing diagrams provide the information about the various conditions of the

signal while a machine cycle is executed.

T- State : It is one cycle of the clock (clock period)

Machine cycle / Bus cycle :

The group of T-States required for a basic bus operation is called as Machine cycle

The microprocessor uses bus cycles for memory and I/O operations

Opcode fetch cycle

Memory Read cycle

Memory Write cycle

I/O Read cycle

I/O Write cycle

Instruction cycle:

The time required for the microprocessor to fetch, decode & execute an instruction is

called an Instruction cycle.

An instruction cycle consists of one (or) more bus cycles.

The timing diagram for Memory Read cycle in Minimum mode is shown in figure.

During the time period T

The micro processor sends out 20 bit address.

Enables ALE Signal

Issues M/ = 1 for memory operation

Issues DT/ = 0 for data reception

During the time period T

The address information is removed from multiplexed bus and status signals are

placed.

However A0-A19 remain available as they were latched during T

Enables

signal

During the time period T

The microprocessor checks the READY line. If READY =1, the µP reads the data

from data bus. Otherwise, a WAIT state T

is inserted

During the time period T

All the control signals are deactivated to start the next cycle.

, DT/ , M/ and signals are deactivated

The timing diagram for Memory Write cycle in Minimum mode:

1.5. MAXIMUM MODE CONFIGURATION OF 8086 :

The max. mode operation is selected by connecting the pin MN/MX to GND

The 8086 is operated in max. mode in multi-processor system with more than one

processor.

In max. mode, the control signals are generated by external Bus-controller 8288. The

maximum mode operation is used only when the system contains arithmetic co-

processor such as 8087 numeric co-processor.

Max. Mode signals QS

, QS

, ,

, , , RQ/ , RQ/

MAXIMUMMODE SIGNALS:

& QS

(pins-24&25):

The Queue status pins indicate the status of

Instruction Queue of 8086 processor.

, , (pins- 26,27&28):

These status signals indicate the function of the

current bus-cycle. i.e., the type of operation being

carried out by the processor.

Queue

Status

operation

First

byte of Opcode

Queue

is empty

Next byte

of Opcode

Bus

cycle

INTA

I/O

Read

/O Write

HALT

-code fetch

Memory

read

Memory

write

INACTIVE

RQ /

: ( pin-29)

This pin indicates that the processor is executing a LOCK prefixed instruction and

the System bus is not to be used by another bus-master.

This pin is used in multi-processor system to prevent other Bus masters from taking

the control of System bus during the execution of a critical instruction.

, RQ / ( pins -30 & 31) :

The Request/Grant pins are used to request a DMA action during Maximum mode

operation.

Theseare bidirectional and used to request and grant the DMA operation.

Timing diagrams for Max. mode

Op-code fetch cycle

Memory Read cycle

Memory Write cycle

I/O Read cycle

I/O Write cycle

1.6. PHYSICAL MEMORY ORGANIZATION AND

M E M O RY BANKS ACCESSING

The Physical memory of 8086 is divided into TWO banks for accessing 16-bit numbers.

Each bank size is 512 K bytes.

The data bus (D

- D

) is connected to LOW bank /EVEN bank.

The data bus (D

- D

) is connected to HIGH bank/ ODD bank.

Both Banks are enabled at a time for 16-bit operations

Address lines (A

-A

) are used to select a location within the bank

The LOW bank is selected by A

The HIGH bank is selected by signal.

Both Banks are enabled at a time for 16-bit operations.

Note that the address must be EVEN for 16-bit access.

Bank Selected

Both banks

are enabled for 16-bit operation

HIGH

bank is enabled

LOW

bank is enabled

banks are enabled

1.7. INTERRUPTS OF 8086 & INTERRUPT VECTOR TABLE

Interrupt is an event that causes the µp to stop the normal program execution.

The µp services the interrupt by executing a subroutine called Interrupt Service Routine

After executing ISR, the control is transferred back again to the main program.

Thereare 3 sources of interruptsfor8086

Hardware Interrupts

Software Interrupts

Error in program execution

signal applied to NMI, INTR pins

by executing INT instructions

Divide by Zero, Overflow, etc

Hardware Interrupts :

These interrupts occur as signals on the external pins of the microprocessor. 8086 has

two pins to accept hardware interrupts, NMI and INTR.

NMI (Non Maskable Interrupt )

It is a positive going edge triggered Non-Maskable Interrupt

It cannot be disabled by using software.

This interrupt has highest priority than INTR.

On receiving an interrupt on NMI line, the microprocessor executes INT 4

The µp obtains the ISR address from location 2 x 4 = 00008H from the IVT

INTR(Interrupt Request)

It is a level triggered maskable Interrupt Request.

It can be disabled by using software i.e., the processor will get interrupted

only if IF=1. Otherwise the processor will not get interrupted even INTR is

active.

It is masked by making IF = 0 by software through CLI instruction.

It is unmasked by making IF = 1 by software through STI instruction.

It is a non-vectored interrupt. On receiving an interrupt on INTR line, the µp

issues INTA pulse to the interrupting device. Then the interrupting device

multiplies N x 4

and goes to the corresponding location in the IVT to obtain the ISR address.

Software Interrupts :

These interrupts are caused by writing the software interrupt instruction INT N

be invoked by software.

Error conditions :

The 8086 is interrupted when some special conditions occur while executing certain

instructions in the program.

Example: Divide error, Overflow etc

Processing of Interrupts

When an interrupt is enabled, the 8086 µp performs the following actions

It completes the execution of current instruction

It pushes the Flag register (PSW) on to the stack

The contents of CS and IP are pushed to stack (return address)

It issues an Interrupt acknowledge (INTA)

It computes the vector address from the type of interrupt

The IP & CS are loaded with ISR address, which is available in Interrupt Vector Table

Then the control is transferred to ISR and starts to execute the interrupt service

routine at that address.

The code to handle an interrupt is called an interrupt handler or Interrupt Service Routine (ISR). An

interrupt service routine must always finish with the special instruction IRET (return from

interrupt), which performs the following actions.

The IP and CS are loaded with return address from stack

The Flag register is popped from the stack

The program execution returns to main line, where it was interrupted.

Interrupt Vector Table:

When the interrupt is enabled, the present IP and CS are pushed on to the stack and loaded

with the address of ISR, which is available in Interrupt vector table.

Interrupt Vector It is a memory block which contains address of ISR

The size of Interrupt vector is 4-bytes (to store CS and IP of ISR)

Interrupt Vector Table It is a memory block which contains interrupt vectors

Since there are 256 types of interrupts, there are 256 interrupt vectors

Hence, the size of Interrupt Vector Table is 4*256 = 1024 bytes

In 8086 interrupt system, the first 1 KB memory from 00000 H to 003FF H is reserved for

storing the starting addresses of ISRs. This block of memory is called as IVT.

The Interrupt vector table contains 256 interrupt vectors

The interrupt vector contains IP and CS values of ISR

The address of interrupt vector can be calculated by multiplying the TYPE with 4

For example, The interrupt vector address for Type-02 interrupt = 02 H*4= 00008 H

The 8086 uses 256 types of interrupts Type 00 to Type 255

These interrupts are classified as

(A) Dedicated Interrupts (Type 00 to Type 04) : 05

(B) Reserved Interrupts (Type 05 to Type 31) : 27

(A) The dedicated interrupts (Type 0 Type 4) are

(i) INT 0 :

(ii) INT 1 :

(iii) INT 2 :

(iv) INT 3 :

(v) INT 4 :

Divide Error

Single step execution (TRAP)

Non-Maskable Interrupt (NMI)

Break Point

Overflow

(i) INT 0 (Divide Error)-

This interrupt occurs whenever there is division error i.e. when the result of a

division is too large to be stored. This condition normally occurs when the

divisor is very small as compared to the dividend (or) the divisor is zero.

Its ISR address is stored at location: Type 0 x 4 = 00000H in the IVT.

(ii) INT 1 (Single Step)-

The µp executes this interrupt after every instruction if the TF =1

It puts µp in single stepping mode i.e. the microprocessor will get interrupted

after executing every instruction. This is very useful during debugging.

This ISR generally displays contents of all registers.

Its ISR address is stored at location: Type 1 x 4 = 00004H in the IVT.

(iii)

INT 2 (Non Maskable Interrupt)-

The microprocessor executes this ISR in response to an interrupt on the NMI

(Non mask-able Interrupt) line.

Its ISR address is stored at location: Type 2 x 4 = 00008H in the IVT.

(iv) INT 3 (Breakpoint Interrupt)-

This interrupt is used to cause breakpoints in the program.

It is useful in debugging large programs

This ISR generally displays contents of all registers

Its ISR address is stored at location: Type 3 x 4 = 0000CH in the IVT

(v)

INT 4 (Overflow Interrupt)

This interrupt occurs if the overflow flag is set

It is used to detect overflow error in signed arithmetic operations.

Its ISR address is stored at location: Type 4 x 4 = 00010H in the IVT

(B) Reserved interrupts (Type 5 to Type 31)

These levels are reserved by Intel to be used in higher processors like 80386, Pentium

etc. They are not available to the user

These are user defined, software interrupts.

ISRs for these interrupts are written by the users to service various user defined

conditions.

These interrupts are invoked by writing the instruction INT N.

Its ISR address is obtained by the microprocessor from location N x 4 in the IVT

Problem:

The contents of memory location 0000:008C are given below

0000:008C 12, 34, 56, 78, 90, 92

(a) What is the interrupt vector address for Type-23H interrupt?

(b) Find the address of ISR corresponding to INT 23H

Sol: (a)

Interrupt vector address = Type * 4

For Type-23H interrupt, Interrupt vector address =

23*4 = 8C HInterrupt vector address for Type-23H is

0000:008C H

(b) The address of ISR for Type-23H is available at

0000:008C H ISR IPis available at memory

0000:008C H = 3412 HISR CSis available at memory 0000:008E H = 7856 HAddress of ISR

00C8

Type = 00C8 / 4

= Type * 4

= 32H

Hence the Type of Interrupt is 32H